1. Jack Dongarra and Bernard Tourancheau, editors. Cluster and Computational Grids for Scientific Computing, 2009. Parallel Processing Letters. [bibtex-entry]



2. Jack Dongarra and Bernard Tourancheau, editors. Special section: Cluster and computational grids for scientific computing, 2008. Future Generation Comp. Syst. 24 (1). [bibtex-entry]



3. Jack Dongarra and Bernard Tourancheau, editors. Clusters and Computational Grids for Scientific Computing, March 2007. Parallel Processing Letters 17(1). [bibtex-entry]



4. Jack Dongarra and Bernard Tourancheau, editors. Cluster and Computational Grids for Scientific Computing, Special Issue on Tools, 2006. International Journal of High Performance Computing Applications 20(3). [bibtex-entry]



5. CongDuc Pham and Bernard Tourancheau, editors. Grid infrastructures: practice and perspectives., volume 21, 2005. Future Generation Comp. Syst.. [bibtex-entry]



6. Jack Dongarra and Bernard Tourancheau, editors. Cluster and Computational Grids for Scientific Computing, volume 20, 2004. International Journal of High Performance Computing Applications. [bibtex-entry]



7. Jack Dongarra and Bernard Tourancheau, editors. Special issue on Clusters and Computational Grids for Scientific Computing, volume 18, 2004. International Journal of High Performance Computing Applications. [bibtex-entry]



8. Jack Dongarra and Bernard Tourancheau, editors. Cluster and Computational Grids for Scientific Computing, volume 13, 2003. [bibtex-entry]

1. Faycal Bouhafs, Jean-Patrick Gelas, Laurent Lefèvre, Moufida Maimour, CongDuc Pham, Pascale Vicat-Blanc Primet, and Bernard Tourancheau. Designing and evaluating an active grid architecture.. Future Generation Comp. Syst., 21(2):315-330, 2005. [bibtex-entry]



2. P. Geoffray, C. Pham, and B. Tourancheau. A Software Suite for High-Performance Communications on Clusters of SMPs. Journal of Cluster Computing, 5(4):353-363, 2002. [bibtex-entry]



3. G. Montenegro, B. Gaidioz, P. Primet, and B. Tourancheau. Equivalent differentiated services for AODVng. SIGMOBILE Mobile Computing and Communications Review, 6(3), July 2002. [bibtex-entry]



4. G Piganeau, R Westrelin, B Tourancheau, and C Gautier. Multiplicative versus additive selection in relation to genome evolution: a simulation study. Genetical Research, 78:171-175, 2001. [bibtex-entry]



5. Bernard Tourancheau and Roland Westrelin. Study of the medium message performance of BIP/Myrinet. Parallel Processing Letters, 11(2/3):297-309, 2001. [bibtex-entry]



6. Bernard Tourancheau, Laurent Lefèvre, and Cong-Duc Pham. Proceedings of MUG 2000 : First Myrinet User Group Conference. September 2000. [bibtex-entry]



7. Marc Herbert, Frederic Naquin, Loïc Prylli, Bernard Tourancheau, and Roland Westrelin. Protocole pour le Gbit/s en réseau local: l'experience Myrinet. Calculateurs Paralleles, Reseaux et Systemes Repartis, 10(1):35-54, February 1998. [bibtex-entry]



8. Abdelhamid Benaini, Patrice Quinton, Yves Robert, Yannick Saouter, and Bernard Tourancheau. Synthesis of a new systolic architecture for the algebraic path problem. Science of Computer Programming, 15:135-158, 1990. [bibtex-entry]



9. Michel Cosnard, Yves Robert, and Bernard Tourancheau. Evaluating speedups on distributed memory architectures. Parallel Computing, 10:247-253, 1989. [bibtex-entry]



10. Yves Robert, Bernard Tourancheau, and Gilles Villard. Data allocation strategies for the Gauss and Jordan algorithms on a ring of processors. Information Processing Letters, 31:21-29, 1989. [bibtex-entry]



11. Yves Robert and Bernard Tourancheau. Block Gaussian elimination on a hypercube vector multiprocessor. Revista de Matematicas Aplicadas, 10:49-69, 1989. [bibtex-entry]



12. Yves Robert, Bernard Tourancheau, and Gilles Villard. Algorithmes de Gauss et de Jordan sur un anneau de processeurs. C. R. Acad. Sc. Paris, série I, 309:403-406, 1989. [bibtex-entry]

1. Leila Ben Saad and Bernard Tourancheau. Multiple Mobile Sinks Positioning in Wireless Sensor Networks for Buildings. In SensorComm, 2009. IEEE-IARIA. [bibtex-entry]



2. Yannis Mazzer and Bernard Tourancheau. Comparisons for 6LoWPAN Implementation on Wireless Sensor Networks. In SensorComm, 2009. IEEE-IARIA. [bibtex-entry]



3. Bernard Tourancheau, Yannis Mazzer, Gérard Krauss, Valentin Marvan, and Frederic Kuznick. Software Calibration of Wirelessly Networked Sensors. In SensorComm, 2009. IEEE-IARIA. [bibtex-entry]



4. Yannis Mazzer and Bernard Tourancheau. MPI in Wireless Sensor Networks. In PVM/MPI Recent Advances in Parallel Virtual Machine and Message Passing Interface, volume 5205 of Lecture Notes in Computer Science, pages 334-339, 2008. Springer. [bibtex-entry]



5. Bernard Tourancheau, Gérard Krauss, and Richard Blanchard. Parametric Sensitivity Study and Optimization of the SDHW and PV Subsystems in an Energy Positive House. In IBPSA-France, 2008. [bibtex-entry]



6. Bernard Tourancheau, Yannis Mazzer, Gérard Krauss, Valentin Marvan, and Frederic Kuznick. Calibration of sensors embedded on a micro-controler based wireless network. In IBPSA-France, 2008. [bibtex-entry]



7. Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, and Ivan E. Sutherland. Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication.. In Hot Interconnects, IEEE Symposium on High Performance Interconnects, pages 13-22, 2005. IEEE Computer Society. [bibtex-entry]



8. Nicolas Fugier, Éric Lemoine, Marc Herbert, and Bernard Tourancheau. MPI for the Clint Gb/s interconnect, A hardware/software design experience. In Recent Advances in Parallel Virtual Machine and Message Passing Interface, LNCS, Venice, Italy, September 2003. Springer-Verlag. [bibtex-entry]



9. Marc Herbert, Pascale Primet, Bernard Tourancheau, and Laurent Lefevre. A scalable and fully distributed architecture for Ethernet switching. In Proceedings of the 2002 Workshop on High Performance Switching and Routing (HPSR 2002), Kobe, Hyogo pref., Japan, pages 234--238, May 2002. IEICE Communication Society, IEEE. [bibtex-entry]



10. Benjamin Gaidioz, Pascale Primet, and Bernard Tourancheau. Differentiated Fairness: Model and Implementation. In HPSR : High Performance Switching and Routing, Dallas, USA, pages 260--264, May 2001. IEEE. [bibtex-entry]



11. P. Geoffray, C. Pham, L. Prylli, B. Tourancheau, and R. Westrelin. Protocols and Software for Exploiting Myrinet Clusters. In Proceedings of the International Conference on Computational Science (ICCS 2001), number 2073&2074 of LNCS, San Francisco, CA, USA, pages 233-242, May 2001. Springer-Verlag. [bibtex-entry]



12. L. Lefèvre, C. Pham, P. Primet, B. Tourancheau, B. Gaidioz, J.P. Gelas, and M. Maimour. Active Networking Support for the Grid. In Noaki Wakamiya Ian W. Marshall, Scott Nettles, editor, IFIP-TC6 Third International Working Conference on Active Networks, IWAN 2001, volume 2207 of Lecture Notes in Computer Science, pages 16-33, October 2001.
    Note: ISBN: 3-540-42678-7. [bibtex-entry]



13. Bernard Tourancheau and Roland Westrelin. Support for MPI at the network interface level. In 8th European PVM/MPI Users Group Meeting, volume 2131, Santorini (Thera) Island, Greece, pages 52-60, September 2001. Springer - Verlag. [bibtex-entry]



14. Benjamin Gaidioz, Rich Wolski, and Bernard Tourancheau. Synchronizing Network Probes to avoid Measurement Intrusiveness with the Network Weather Service. In Proceedings of HPDC : High Performance Distributed Computing, Pittsburgh, USA, pages 147--154, August 2000. IEEE. [bibtex-entry]



15. Patrick Geoffray and Bernard Tourancheau. Optimiser la latence du broadcast MPI pour les reseaux locaux haute performance. In INRIA Press, editor, Algotel 2000, La Rochelle, France, May 2000. [bibtex-entry]



16. Bernard Tourancheau and Roland Westrelin. Study of the medium message performance of BIP/Myrinet. In IEEE International Conference on Cluster Computing (CLUSTER 2000), Chemnitz, Germany, November 2000. IEEE Society Press. [bibtex-entry]



17. P. Geoffray, L. Lefèvre, C. Pham, L. Prylli, O. Reymann, B. Tourancheau, and R. Westrelin. High-Speed LANs: New Environments for Parallel and Distributed Applications. In ACM/IFIP EuroPar'99, number 1685 of LNCS, Toulouse, France, pages 633-642, August 1999. Springer-Verlag. [bibtex-entry]



18. P. Geoffray, C. D. Pham, and B. Tourancheau. Exploiting Clusters of Shared Memory Multiprocessors with BIP-SMP: the Parallel Simulation Application. In N. P. Carter and S. S. Lumetta, editors, ACM International Conference on Supercomputing (ICS'99), Workshop on Cluster-based Computing, Rhodes, Greece, June 1999. [bibtex-entry]



19. Patrick Geoffray, Loïc Prylli, and Bernard Tourancheau. BIP-SMP: High Performance message passing over a cluster of commodity SMPs. In Supercomputing (SC '99), Portland, OR, November 1999.
    Note: Electronic proceedings only. [bibtex-entry]



20. Loïc Prylli, Bernard Tourancheau, and Roland Westrelin. The Design for a High Performance MPI Implementation on the Myrinet Network. In Recent Advances in Parallel Virtual Machine and Message Passing Interface. Proc. 6th European PVM/MPI Users' Group (EuroPVM/MPI '99), volume 1697 of Lect. Notes in Comp. Science, Barcelona, Spain, pages 223-230, September 1999. Springer Verlag. [bibtex-entry]



21. Loïc Prylli, Bernard Tourancheau, and Roland Westrelin. An Improved NIC Program for High-Performance MPI. In Workshop on Cluster-Based Computing. International Conference on Supercomputing, Rhodes, Greece, pages 26-30, June 1999. ACM ICS.
    Note: Electronic proceedings only, at http://www.crhc.uiuc.edu/ steve/wcbc99/. [bibtex-entry]



22. Loic Prylli and Bernard Tourancheau. BIP: a new protocol designed for high performance networking on Myrinet. In Workshop PC-NOW, IPPS/SPDP98, Orlando, USA, 1998. [bibtex-entry]



23. Loïc Prylli, Bernard Tourancheau, and Roland Westrelin. Modeling of a high speed network to maximize throughput performance: the experience of BIP over Myrinet. In H.R. Arabnia, editor, Parallel and Distributed Processing Techniques and Applications (PDPTA '98), volume II, Las Vegas, USA, pages 341-349, 1998. CSREA Press. [bibtex-entry]



24. Lionel Brunie, Serge Chaumette, Michel Cosnard, Frédéric Desprez, Laurent Lefèvre, Michel Loi, Bernard Tourancheau, Xavier Vigouroux, and Makan Pourzandi. The LHPC Programming Environment. In SIAM : Society for Industrial and Applied Mathematics, editors, Proceedings of the Second Workshop on Environments and Tools for Parallel Scientific Computing, Townsend, TN, USA, May 1994. [bibtex-entry]



25. Yves Robert and Bernard Tourancheau. Linear algebra algorithms on distributed memory machines. In J. G. McWhirter, editor, Mathematics in Signal Processing II, pages 665-687, 1990. Clarendon Press. [bibtex-entry]



26. Abdelhamid Benaini, Yves Robert, and Bernard Tourancheau. A new systolic architecture for the algebraic path problem. In J.M. Canny et al., editor, Systolic Array Processors, pages 73-82, 1989. Prentice Hall. [bibtex-entry]



27. Yves Robert and Bernard Tourancheau. Impact of the architecture topology on data allocation strategies for Gaussian elimination on the hypercube. In 4-th Conf. on Hypercube Concurrent Computers and Applications, pages 693-696, 1989. Sandia National Laboratories Press. [bibtex-entry]



28. Yves Robert and Bernard Tourancheau. LU and QR factorization on the FPS T Series hypercube. In C.R. Jesshope and K.D. Reinartz, editors, CONPAR 88, pages 516-525, 1989. Cambridge University Press. [bibtex-entry]

1. Yannis Mazzer and Bernard Tourancheau. Réseaux de micro-contrôleurs à faible consommation d'énergie embarquant des capteurs. Technical report 00256210, INRIA, janvier 2008. [bibtex-entry]



2. Laurent Lefèvre, Eric Lemoine, Cong-Duc Pham, and Bernard Tourancheau. Fast forwarding with network processors. Technical report RR-4710, INRIA, January 2003. [bibtex-entry]

1. Hans Eberle, Nils Gura, Nicolas Fugier, and Bernard Tourancheau. Method and Apparatus for Speculative Arbitration. US Patent 7352741, 2008. [bibtex-entry]



2. Bernard Tourancheau, Ronald Ho, and Robert Drost. Method and Apparatus for Performing Error-Detection and Error-Correction. US Patent 7395483, 2008. [bibtex-entry]



3. Bernard Tourancheau. Method and apparatus for routing data across an n-dimensional grid network. US Patent 7444424, 2008. [bibtex-entry]



4. Bernard Tourancheau, Francois Vigouroux, and Cedric Koch-Hofer. System and method for determining a carrier layout using cornered chip-to-chip input/output. US Patent 7191422, 2007. [bibtex-entry]



5. Jo Ebergen, Ivan Sutherland, and Bernard Tourancheau. Arbiters with Preferential Enables for Asynchronous Circuits. US Patent 7064583, 2006. [bibtex-entry]



6. Francois Vigouroux, Bernard Tourancheau, and Cedric Koch-Hofer. Network chip design for grid communication. US Patent Application 0224796, 2006. [bibtex-entry]



7. Francois Vigouroux, Bernard Tourancheau, and Cedric Koch-Hofer. Optimal communication path routing in a system employing interconnected integrated circuit technology. US Patent Application 0018261, 2006. [bibtex-entry]

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