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Project Description

The multicore revolution is underway, bringing new chips introducing more complex memory architectures. Classical algorithms must be revisited in order to take the hierarchical memory layout into account. In REF, we introduce cache-aware algorithms that minimize the number of cache misses paid during the execution of the matrix product kernel on a multicore processor. We analytically show how to achieve the best possible tradeoff between shared and distributed caches.

We implement and evaluate several algorithms on two multicore platforms, one equipped with one Xeon quadcore, and the second one enriched with a GPU. It turns out that the impact of cache misses is very different across both platforms, and we identify what are the main design parameters that lead to peak performance for each target hardware configuration.

Documentation

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Source Code
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Related Papers
Download pdf Mathias Jacquelin, Loris Marchal, and Yves Robert. The impact of cache misses on the performance of matrix product algorithms on multicore platforms.Research report, RR INRIA 7456, LIP, ENS Lyon, 2010.

[Bibtex]

@techreport{JACQUELIN:2010:INRIA-00537822:1, HAL_ID = {inria-00537822}, URL = {http://hal.inria.fr/inria-00537822/en/}, title = { {T}he impact of cache misses on the performance of matrix product algorithms on multicore platforms}, author = {{J}acquelin, {M}athias and {M}archal, {L}oris and {R}obert, {Y}ves}, keywords = {{M}ulticore platform; {M}atrix product; {C}ache misses; {C}ache-aware algorithms}, language = {{E}nglish}, affiliation = {{GRAAL} - {INRIA} {G}renoble {R}h{\^o}ne-{A}lpes / {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {CNRS} : {UMR}5668 - {INRIA} - {\'E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - {L}aboratoire d'informatique du {P}arall{\'e}lisme }, pages = {32 }, type = {{R}esearch {R}eport}, institution = {INRIA}, number = {{RR}-7456}, day = {19}, month = {11}, year = {2010}, URL = {http://hal.inria.fr/inria-00537822/PDF/RR-7456.pdf}, }
Mathias Jacquelin, Loris Marchal and Yves Robert. Complexity analysis and performance evaluation of matrix product on multicore architectures. In ICPP'2009, the 38th International Conference on Parallel Processing, 2009, IEEE Computer Society Press.

[Bibtex]

@inproceedings{DBLP:conf/icpp/JacquelinMR09,
author = {Mathias Jacquelin and
Loris Marchal and
Yves Robert},
title = {Complexity Analysis and Performance Evaluation of Matrix
Product on Multicore Architectures},
booktitle = {ICPP},
year = {2009},
pages = {196-203},
ee = {http://doi.ieeecomputersociety.org/10.1109/ICPP.2009.40},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Download pdf Mathias Jacquelin, Loris Marchal and Yves Robert. Complexity analysis and performance evaluation of matrix product on multicore architectures. Research report, RRLIP2009-09, LIP, ENS Lyon, 2009.

[Bibtex]

%% ensl-00381458, version 1
%% http://prunel.ccsd.cnrs.fr/ensl-00381458/en/
@unpublished{JACQUELIN:2009:ENSL-00381458:1,
title={{C}omplexity analysis and performance evaluation of matrix product on multicore architectures},
author={{J}acquelin, {M}athias and {M}archal, {L}oris and {R}obert, {Y}ves},
abstract={{T}he multicore revolution is underway, bringing new chips introducing more complex memory architectures. {C}lassical algorithms must be revisited in order to take the hierarchical memory layout into account. {I}n this paper, we aim at minimizing the number of cache misses paid during the execution of the matrix product kernel on a multicore processor, and we show how to achieve the best possible tradeoff between shared and distributed caches. {C}omprehensive simulation results confirm the analytical performance predictions and fully establish the practical significance of our new algorithms.},
keywords={algorithm;matrix product;multicore},
language={{A}nglais},
affiliation={{GRAAL} - {INRIA} {R}h{\^o}ne-{A}lpes / {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {CNRS} : {UMR}5668 - {INRIA} - {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon - {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - {L}aboratoire d'informatique du {P}arall{\'e}lisme - {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {LIP} - {INRIA} - {CNRS} : {UMR}5668 - {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon },
note={nombre de pages: 25 {RRLIP}2009-09 },
URL={http://prunel.ccsd.cnrs.fr/ensl-00381458/en/},
}